1. Field of the Invention
The present invention relates generally to electrical circuits, and more particularly, to methods and systems for balancing precharging delays when precharging bitlines of a banked memory array of memory cells.
2. Description of the Related Art
In memory circuits, current designs of precharge circuits can exhibit performance limitations due to the arrangement of memory cells on bitlines. FIG. 1A shows a precharge circuit 100 with an array of memory cells organized in rows and columns. The first row 102 contains memory cells, such as, for example, cell 104, cell 106, and cell 108. The array contains a series of rows, such as second row 110 and so on. Memory cell 104 is connected to a bitline 112, indicated by a dash mark where memory cell 104 and bitline 112 intersect. As is well known, bitlines, such as bitline 112 allows the reading of the data stored in memory cell 104. Write bitlines, which are not shown, would allow the writing of data to the memory cell 104. The memory cells located in the column formed below memory cell 104 are also connected to bitline 112. Bitline 112 is connected to sense amp 116 and precharge device 114 is attached to bitline 112. The precharge device 114 precharges the associated bitline 112.
As the number of memory cells attached to a bitline increases, problems can occur due to leakage from the memory cells (i.e., the load impact of each memory cell being coupled to the same long bitline). For example, if the leakage is too great from the memory cells attached to bitline 112, the precharge device 114 must be increased in drive strength so as to efficiently precharge the bitline 112. It is important to note that as the number of memory cells coupled to the bitline 112 increases, this load increase will necessarily increase the time it takes the bitline 112 to reach the designed precharge voltage level. This increase in time therefore reduces the speed of the memory access operation, thus reducing memory performance.
One approach to this problem is to decrease the size of the column of memory cells supported by a bitline by decreasing the number of rows in the memory array. When the number of rows of memory cells is greater than some number, the array is typically broken down into smaller arrays. As shown in FIG. 1B, a precharge circuit 122 is coupled to a top array 124 and a bottom array 134, each having half the memory cells. For exemplary purposes, one memory cell is coupled through a load transistor 126 (which is in the top array 124). Connections to other memory cells to bitline 128 is shown by dashed lines on bitline 128. Likewise, one memory cell is coupled through a load transistor 136 (which is in the bottom array 134). The memory cells of the top array 124 and the bottom array 134 are combined using a sense amp 130, which includes an AND logic operator, and the resulting output is sent out on wire 140 to the receiving circuitry not shown. Each bitline has its own precharge circuit. Bitline 128 is connected to precharge device 122 while bitline 138 is connected to precharge device 132. Now each precharge device provides charge to half the memory cells, whereas in FIG. 1A, one precharge device was providing charge to all memory cells in the column. The precharge devices 122 and 132 of FIG. 1B can now be sized smaller. Also since each bitline (128 and 138) has fewer memory cells to support the bitline loading is lower and the risk of leakage decreases. More wire is needed for this configuration, compared to FIG. 1A, since the ouput must be brought down from the sense amp 130 to the receiving circuitry (now shown). Splitting the array of FIG. 1A into smaller arrays as seen in FIG. 1B reduces the bitline loading, the leakage, and the size of the precharge devices, but increases the complexity and can sometimes be impossible due to substantial area increases for additional circuitry.
Another configuration of a precharge device 150 where memory cells are split across two arrays (banks) is shown in FIG. 1C. The top array 154 and bottom array 164 each have half the memory cells. Each bitline has its own precharge device. Bitline 158 is connected to precharge device 152 while bitline 168 is connected to precharge device 162. The memory cells of the top array 154 and the bottom array 164 are combined using a sense amp 160, which includes AND logic. As the sense amp 160 has an anding operation, the resulting output is sent out on wire 170 to the receiving circuitry not shown. To bring the output from the upper array 154 down to the sense amp 160 requires extra wire, which is traveling down and across the lower array 164 to the sense amp 160. Since it has extra wire to support, precharge device 152 must be larger than precharge device 162. Here, the precharge timing has to be tuned based on two circuits instead of one and the relative timing must be match. Matching here is very complicated to accomplish since these two precharge circuits have different lengths of wire and precharge devices of different sizes.
Since the two precharge circuits will usually not be balanced, there will be a delay mismatch in the delivery of the signal from the bitlines to the sense amp 160. With two sets of precharge circuits, the timing requirements between the precharge and other signals also becomes more complicated. Additionally since the margin (i.e., the time frame for error) is becoming tighter in newer designs, the difficulty in balancing the mismatch grows considerably.
In another prior art design shown by FIG. 1D, the precharge circuit 180 again contains memory cells split across a top array 184 and a bottom array 194. The sense amp 200 is located below the bottom array 194, and the accompanying precharge devices are both located above the top array 184. In this configuration there could still be a delay mismatch because of the arrangement of the memory cells and wire is not in the same order from each precharge device. FIG. 1F schematically illustrates the effect of the arrangement of wire and devices. Schematic 300 represents bitline 188 from FIG. 1D and schematic 320 represents bitline 198 from FIG. 1D. In schematic 300, the capacitor in dashed block 302 represents the capacitive value of the devices (such as the memory cells and the precharge device) attached to bitline 188 in FIG. 1D. The resistors and capacitor in dashed block 304 represent the resistive and capacitive value of the wire of bitline 188 that extends across array 194. In schematic 320, the resistors and capacitor in dashed block 322 represent the resistive and capacitive value of the wire of bitline 198 that extends across array 184. The capacitor in dashed block 324 represents the capacitive value of the devices (such as the precharge device and the memory cells) attached to bitline 198 in FIG. 1D. As can be seen, delay one, D1 from schematic 300 will generally not equal Delay two, D2 of schematic 320. The values of D1 and D2 may be close in size, but they will not be the same. The distribution is different because the arrangement of the capacitors and the resistors will cause a difference in the size of the ultimate delay across the two bitline segments represented. Also, splitting the array to make array banks can provide the benefit of making precharge circuits smaller, but it will require more space for the additional circuitry.
In view of the foregoing, there is a need for memory designs and circuits for balancing precharge delivered to bitlines that couple to memory cells in banked architectures.